Remote

• AMS Verification 6+

Months Contract AMS Verification Job Description Guidance:

Emphasize top-level integration and simulation expertise. Require knowledge in both functional and transistor-level simulation, particularly in Verilog and AMS (Analog/Mixed-Signal) level. Experience in AMS Design of LSFR, Divider path, PFD Charge Pump, New filters, multiple muxes. Essential familiarity with EDA tools, especially Cadence Virtuoso, Verilog simulations, Innovus, and Janus for timing analysis. The new person will work closely with the current team lead on integration and chip-level simulations. Need someone who knows top level integration and simulation, especially functional, Verilog and AMS level. Need someone who knows both transistor level simulations as well as the functional verification simulations for ams. Need someone who can design LSFR circuitry, Divider path circuitry, PFD Charge Pump, New filters, multiple muxes. This is top level . This Engineer needs experience in chip level simulation and will work closely with the lead on various aspects of the work, including the integration. Position #1

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ASIC UVM Verification Location:

Remote Duration:

6-9+ months

Interview Process:

1

Interviews Skills/JD:

UVM/System Verilog Verification. SOC/Sub System Verification. Experience with C Coding is ideal. Experience with High-Speed IP's such as PCIe, DDR, USB. Experience with NOC's, Fabric, or Interconnects is ideal. Position 2:

ASIC Emulation Engineer Location:

onsite in San jose,

CA Duration:

6-9 months

Interview Process:

2 interviews

Skills/JD:

Emulation

• Palladium/Zebu
• the team uses both platforms. Working on bring up of IO's
• PCIe, Ethernet, High Speed interfaces Will build and compile emulation systems.

Integrating Verification testbenches into system. Strong Verilog/System Verilog, Scripting. RTL Design FPEG design Hardware board design

Physical Design Pay:

$57,000.00

• $68,800.

00 per year

Work Location:

In person