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AUREXIS TECH PTE. LTD.

Senior / IC Design Engineer (Design Verification)

Pay: $92,031/yr

Posted: 07/02/2026

Location: Hauppauge, NY (Onsite)

Last Updated: 6 days ago

Hours: Full-Time

Expires: 9/27/2026

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What they do

A Verification Engineer is responsible for ensuring that a product meets its specifications and requirements. Designs methods to test products, identify bugs in software products, and communicates with cross-functional teams, ensuring product development procedures and outcomes meets regulations. Primary objective is to verify that the system functions correctly and reliably according to its design and intended purpose.

$126,730 / year median in New York

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Job Description

AUREXIS TECH PTE. LTD.

Senior / IC Design Engineer (Design Verification)

MCF-2026-1125013

Islandwide Full Time Professional 1 year exp Engineering, Sciences / Laboratory / R D $5,000to$10,000 Monthly 1 applicationPosted 01 Jul 2026Closing on 31 Jul 2026 Roles & Responsibilities Job Description Develop and execute verification plans for Pre-Silicon IP/ASIC/SoC designs based on design specifications. Build and maintain SystemVerilog/ UVM-based verification environments and testbenches Develop directed and constrained-random tests, assertions(SVA), and functional coverage. Debug DUT issues, analyze simulation results, and drive verification closure. Collaborate with cross-functional teams throughout the design and verification lifecycle. Support regression automation and continuously improve verification methodologies. Leverage AI-assisted tools and data-driven techniques to enhance verification efficiency, coverage, and debug productivity. Requirements Bachelor's or Master's degree in Electrical, Electronic, Computer Engineering or related field with at least 1 year of experience. Hands-on experience in ASIC/SoC/IP verification using SystemVerilog and UVM. Knowledge of constrained-random verification, assertions (SVA), functional coverage, and scripting languages such as Python/ Perl/ Tcl. Experience with industry-standard EDA tools (e.g., Cadence or Synopsys). Familiarity with AI/ML-assisted EDA tools or the use of generative AI to improve verification workflows is an advantage. Strong analytical, problem-solving, and communication skills. We invite qualified candidates to apply online or submit a detailed resume to resume@aurexis-tech.com .