Model processor SoC power for a range of workloads; generate power constrained performance projections. Contribute to SoC architecture definition based on modeling results Augment and track power modeling for IP's and SoC's across generations Collaborate with RTL and physical design teams to propose power optimization techniques and drive power convergence at the SoC level. Collaborate with silicon manufacturing and validation teams on post-Si planning, guidance, projection, and debug. Evaluate PnP impact of power management features in pre-Si and post-Si. Opportunistic contributions to power management solutions and implementations. Doctorate in Electrical Engineering, Computer Engineering, Computer Science, or related field AND 3+ years technical engineering experience OR Master's Degree in Electrical Engineering, Computer Engineering, Computer Science, or related field AND 6+ years technical engineering experience OR Bachelor's Degree in Electrical Engineering, Computer Engineering, Computer Science, or related field AND 8+ years technical engineering experience OR equivalent experience. This role will require access to information that is controlled for export under export control regulations, potentially under the U.S. International Traffic in Arms Regulations or Export Administration Regulations, the EU Dual Use Regulation, and/or other export control regulations. As a condition of employment, the successful candidate will be required to provide either proof of their country of citizenship or proof of their US. residency or other protected status (e.g., under 8 U.S.C. 1324b(a)(3)) for assessment of eligibility to access the export-controlled information. To meet this legal requirement, and as a condition of employment, the successful candidate's citizenship will be verified with a valid passport. Lawful permanent residents, refugees, and asylees may verify status using other documents, where applicable. Deep understanding of SoC power contributors and considerations. Understanding of power modeling and power constrained performance Understanding of silicon process as it pertains to SoC power High level understanding of datacenter processor SoC architecture Experience with power management mechanisms