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IP Integration Engineer
Career Insights for Verification Engineer
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What they do
A Verification Engineer is responsible for ensuring that a product meets its specifications and requirements. Designs methods to test products, identify bugs in software products, and communicates with cross-functional teams, ensuring product development procedures and outcomes meets regulations. Primary objective is to verify that the system functions correctly and reliably according to its design and intended purpose.
$158,679 / year median in California
Job Description
At Apple, we work every single day to craft products that enrich people's lives. Do you love working on challenges that no one has solved yet? Do you like changing the game? We have an opportunity for a forward-thinking and especially motivated Analog Mixed Signal IP Integration Engineer! As a member of our dynamic group, you will have the rare and great opportunity to work on upcoming products that will delight and encourage millions of Apple's customers every day! Description In this highly visible role, you will support the integration of 3rd party IP in the SOCs developed by Apple. Your job is to verify that the IP deliverables are meeting Apple's high quality standards and get flawlessly integrated. The role involves working closely with different cross-functional teams within Apple as well as with external vendors. Occasional travel might be required. Minimum Qualifications BS degree in technical subject area and a minimum 10 years relevant industry experience. Preferred Qualifications Experience with Verilog modeling and model validation is a plus Experience with standards like PCI Express, MIPI, USB or DisplayPort is a plus Excellent written and verbal communication skills Strong initiative and ownership of responsibilities, productive, able to meet aggressive deadlines Experience in RTL design, verification or integration Deep knowledge and experience with front-end tools such as simulation, synthesis, lint, logic equivalence, static timing analysis, CDC, RDC, and UPF Familiarity with SOC design flow and verification methodologies Good understanding of DFT requirements for SOCs Experience writing Verilog, SystemVerilog, SVA hardware description languages