Advanced ASIC FPGA Design Engineer Position Available In Guilford, North Carolina

Advanced

ASIC FPGA

Design Engineer ID:

550355

Posted:

5/8/2025

Location:

McLeansville, NC

Category:

Pro – Engineering

Job Type:

Temp to Direct

Duration:

Contract to Di Description ACARA Solutions and our client in McLeansville, NC have a contract-to-hire position available FPGA Design Engineer We encourage you to if you have any of these preferred skills or experiences: Experience with VHDL/Verilog/SystemVerilog and TCL or similar languages, Zync UltraScale+ MPSoC or similar FPGAs, Vivado or similar tools.

Knowledge, Skills and Abilities:

Proficient in the principles and techniques of FPGA design. Keeps abreast of technology trends.
Proficient written and verbal communications skills, ability to think creatively, and multi-task.
Proficient skill in communicating issues, impacts, and corrective actions.
Works under limited direction. Regular contact with senior levels of internal work groups. Contact with project leaders and other professionals within the Engineering department and with project teams across the company. Some contact with external customers.

What sets you apart:

Experience with Multi-Gigabit Transceivers (MGTs): GTX/GTH/GTY/GTZ/etc…
Experience with bus protocols like: 1G/10G/40G Ethernet, SONET, OTN, EtherCAT, RS-232, SPI, I2C, and CAN.
Experience working with time critical or low latency designs with PTP/SyncE or synchronous industrial networks like EtherCAT and Sercos III
Experience with packet or signal processing
Experience interfacing to external memory interfaces like:

DRAM / SRAM.

Experience with Zynq processors using Petalinux, Yocto, or Buildroot.
Experience with Git for version control and CI/CD flows for FPGA.
Understanding of static timing analysis, timing closure and floor planning techniques for designs that include but are not limited to custom developed solutions with embedded hard & soft processors and with commercial & custom IP.
Understanding of communication link design: including equalization techniques, FEC, filtering, and clock recovery Job Requirements Required Skills /

Qualifications:

Bachelor’s Degree in Electrical or Computer Engineering or Science or Engineering or Mathematics.
Minimum of 5 years of experience with VHDL/Verilog/SystemVerilog and TCL or similar languages, Zync UltraScale+ MPSoC or similar FPGAs, Vivado or similar tools.
Minimum of 5 years of experience with Multi-Gigabit Transceivers (MGTs):

GTX/GTH/GTY/GTZ.

Minimum of 5 years of experience with bus protocols like: 1G/10G/40G Ethernet, SONET, OTN, EtherCAT, RS-232, SPI, I2C, and CAN.
Minimum of 5 years of experience working with time-critical or low-latency designs with PTP/SyncE or synchronous industrial networks like EtherCAT and Sercos III.
Minimum of 5 years of experience with packet or signal processing.
Minimum of 5 years of experience interfacing with external memory interfaces like

DRAM / SRAM.

Minimum of 5 years of experience with Zynq processors using Petalinux, Yocto, or Buildroot.
Minimum of 5 years of experience with Git for version control and CI/CD flows for FPGA. Preferred Skills /

Qualifications:

Master’s Degree.
Proficient in the principles and techniques of FPGA design.
Proficient written and verbal communication skills, ability to think creatively, and multi-task.
Proficient in communicating issues, impacts, and corrective actions.
Understand static timing analysis, timing closure, and floor planning techniques for designs that include, but are not limited to, custom-developed solutions with embedded hard and soft processors and commercial and custom IP.
Understanding communication link design, including equalization techniques, FEC, filtering, and clock recovery.