UVM Digital Verification Engineer Position Available In Suffolk, Massachusetts

Job Description Summary:

Draper’s Digital Design Team is seeking a motivated and experienced UVM Digital Verification Engineer to tackle novel verification challenges in FPGAs and ASICs. In this role, you will apply modern verification strategies to complex digital and mixed-signal designs in the areas of embedded security, cryptography, signal and image processing, navigation and communications.

Job Description:

Duties/Responsibilities + Design and simulate circuits at transistor-level to implement architecture and requirement specifications + Contribute to system-level design + Optimize hardware designs for performance, power, and cost + Evaluate the hardware feasibility of complex algorithms and requirements + Independently contribute to complex chip architectures and designs + Independently drive solutions to complex problems – develop requirements, propose ways forward when customer requirements are unclear or incomplete, and adapt appropriately to changes in requirements + Contribute to business development and proposal activities + Develop, document, and teach best practices to less experienced engineers + Perform or guide physical layout, including floor-planning, and simulate circuits using extracted parasitics. + Perform other duties as assigned Skills/Abilities + Proficiency in integrated circuit design + Understanding of integrated circuits, semiconductors, and general computer architecture + Ability to write detailed design specifications + Ability to manage small technical teams + Excellent verbal and written communication skills + Excellent mathematical skills + Excellent organizational skills and attention to detail + Excellent time management skills with the proven ability to meet deadlines + Strong analytical and problem-solving skills + Ability to prioritize tasks + Demonstrate strong organization, planning, and time management skills to achieve program goals Education + Requires a bachelor’s degree in Engineering, or related field. Masters degree preferred. Experience + Requires 5-7 years of experience with a bachelor’s degree, or 3-5 years of experience with a master’s degree, or 0-2 years of experience with a PhD in ASIC Hardware Engineering or related.

Additional Job Description:

You will develop verification approaches, author and execute verification plans, and use formal analysis tools. You will work in multi-disciplinary teams with opportunities to learn, grow and contribute to a variety of projects. Join us as we develop the next generation of digital and embedded hardware platforms. + Develop verification and test plans + Develop UVM Agents for proprietary buses + Instantiate VIPs for industry standard buses + Work in both block-level/chip-level UVM testbench environment + Work with RTL designers to resolve simulation issues + Implement cover groups according to design requirements + Work on code and functional coverage closures to achieve 100% + Perform code reviews and to mentor junior engineers in the group + Fluent in System Verilog including SVA + Recent experience with

UVM/UVMF

+ Familiarity with at least one major industry simulator (Questasim, Xcelium, VCS) + Familiarity with at least one IEEE bus standard Experience with DDR3/DDR4, Amba Axi protocols + Firm grasp of constrained-random testing and coverage-driven verification + Experience with formal analysis + Practice using Python, Perl, Bash or other scripting languages + Ability to work in a Linux environment + Strong analysis and problem-solving skills Applicants selected for this position will have or be able to obtain and maintain a government security clearance.